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ST5481
L.O.U.I.S - LOW COST USB ISDN SOLUTION
PRODUCT PREVIEW
HARDWARE FEATURES S/T ISDN Interface
s COMMUNICATION DEVICE CLASS AND
VENDOR REQUESTS
s SUPPORTS OSI LEVEL 1 IN CONFORMANCE WITH UIT-T I.430 FOR BASIC ACCESS AT S AND T INTERFACES (ETSI 300012/ANSI T1.605)
s BUS OR SELF POWERED APPLICATION
(PIN PROGRAMMABLE)
s ONNOW POWER MANAGEMENT (D0,D2,D3)
SUSPEND MODE COMPLIANCE
s LINE INTERFACE TRANSFORMER DIRECT
DRIVE
s PIN PROGRAMMABLE HIGH/LOW POWER
USB DEVICE REGISTRATION, WAKE-UP CAPABILITY, USB DEVICE IDENTIFICATION GENERAL - USB hot plug and play interface. - Control access and interrupt handling provided through the USB interface. - All FIFOS and FIFOS management needed included for USB/ISDN data processing. - Internal PLL to generate the USB 48MHz clock from a 15.36MHz crystal. - Internal regulator for 3.3V generation from USB bus 5V. - 48 pin TQFP package. - 0.35 micron HCMOS 6 process. DESCRIPTION ST5481 combines ISDN link access and an USB interface to allow a very simple USB/ISDN modem design with all ISDN protocols and upper applications processed into the HOST PC.
s FULL-DUPLEX TRANSMISSION AT 192KBps
ON SEPARATE TRANSMIT AND RECEIVE TWISTED PAIRS USING ALTERNATE MARK INVERSION (AMI) LINE CODING
s 2 B CHANNELS AT 64KBps EACH PLUS 1 D
CHANNEL AT 16KBps
s ALL
I.430 WIRING CONFIGURATIONS SUPPORTED INCLUDING PASSIVE BUS FOR TE'S DISTRIBUTED POINT TO POINT AND POINT TO MULTIPOINT
s MULTIFRAME SUPPORT s ANALOG
PART: INCLUDED WITH ADAPTIVE DETECTION THRESHOLD AND EQUALIZER
USB Interface
s USB 1.0 SPECIFICATION FULL COMPLIANCE, 1.1 SPECIFICATION COMPATIBILITY (1.1 POWER MANAGEMENT COMPLIANCE), 12 MBps FULL SPEED
s ON-CHIP
USB DIGITAL PLL
TRANSCEIVER
WITH
s 6 ISOCHRONOUS ENDPOINTS FOR B1,
B2, D CHANNELS ENDPOINT FOR I430 DATA.INTERRUPT TQFP48 ORDERING NUMBER: ST5481 TQF7
s ISDN PROTOCOL AND DATA.CONTROL
ENDPOINT FOR USB STANDARD PLUS VENDOR SPECIFIC REQUEST
October 2000
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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ST5481
1 - GENERAL PURPOSE The ST5481 is a single chip ISDN -BRI with USB Interface low cost controller. The purpose is a low cost ISDN modem for applications like INTERNET ACCES and FAX capabilities when the PC is ON (full operating mode). The bonus is to offer an easy and lowcost access to INTERNET at a rate of 128kbits/sec. EASY access due to plug and play features via USB bus and lowcost due to host processing concept and remote powering via USB bus features. 2 - MAIN FUNCTIONS The device controls the S0 ISDN basic rate access (ITU normalization I430) and manages the B1, B2, D channels through the USB bus. B1, B2, D channels data flow is regulated through FIFO memories of respectively 32, 32, 16 bytes in each direction. On D, B1, B2 channels, all upper protocols than basic HDLC framing protocol are host processed from upper-datalink protocol (I440 normalization), network protocol up to 3 - PIN-OUT Figure 1 : Pin-out Synoptic
GNDBUS VREGD1 MODE3 MODE2 MODE1 VREGA RPSM GNDA MOD0 VBUS
applications drivers. Link Activation, deactivation protocols (I430) is managed by the device. But the full handling of the command and indicate primitives is done by the host processor accessing to dedicated registers. Call setup signalling frames through D channel are managed by the host processor. Internal regulators can be enabled to feed the device (and external devices) via the GNDBUS, VBUS USB powering lines. They convert the USB 5 volts to 3.3 volts. The device respects the USB release 1.0 power management recommendations. When entered in suspend mode on USB side the device drop into a low power mode. An internal oscillator and a PLL provide from an external 15.36MHz crystal a 48MHz clock for USB data rate recovering and 15.36MHz clock for S interface. The device offers one operating mode called CLOSED mode plus several test modes. In CLOSED MODE the device presents the USB interface, the S interface and 8 GPIO pins.
12 LIP LIN IREF LON LOP TEST13 TEST12 NCS_TEST11 SDI_TEST10 CFG1_TEST9 SDO_TEST8 SCK_TEST7 13 14 15 16 17 18 19 20 21 22 23 24 25 DX_TEST6
11 10
9
8
7
6
5
4
3
2
DM 1 48 47 46 45 44 43 GPIO7 GPIO6 GPIO5 GPIO4 GNDD1 GPIO3 GPIO2 GPIO1 GPIO0 XTALIN XTALOUT FLTPLL 42 41 40 39 38 37 CFG0/TEST0
ST5481
26 27 DR_TEST5 FS_TEST4
28 29 CLK_TEST3 ID3_TEST2
30 31 ID2_TEST1 ID1_TEST14
32 33 34 ID0_TEST15 VREGD2 NRESET
35 36 GNDD2
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DP
ST5481
3.1 - Pin List
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name DM DP GNDBUS VREGD1 VBUS VREGA GNDA RPSM MODE0 MODE1 MODE2 MODE3 LIP LIN IREF LON LOP TEST13 TEST12 TEST11 TEST10 TEST9 TEST8 TEST7 TEST6 TEST5 TEST4 TEST3 ID3_TEST2 ID2_TEST1 ID1_TEST14 ID0_TEST15 NRESET VREGD2 Type I/O I/O I I/O I I/O I I I I I I In analog In analog In analog Negative USB differential data line Positive USB differential data line USB remote ground Digital input/ output regulated supply, is an input when RPSM is tied to a logic zero value USB remote positive supply 5 volts. 3.3V input/ output analog regulated supply, is an input when RPSM is tied to a logic zero value Analog ground REMOTE POWER SUPPLY MODE: when tied to a logic zero value the device is self powered Static configuration pin. Used for working modes and test modes programming Static configuration pin. Used for working modes and test modes programming Static configuration pin. Used for working modes and test modes programming Static configuration pin. Used for working modes and test modes programming Receive AMI signal differential positive inputs from the S line Receive AMI signal differential negative input from the S line External current reference (connected to an external resistor) Function
Out analog Transmit AMI signal differential negative output to the S line Out analog Transmit AMI signal differential positive output to the S line Out analog Analog test pin: AOPTEST1 Out analog Analog test pin: AOPTEST2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I Test pin Test pin Test pin Test pin Test pin Test pin Test pin Test pin Test pin Either ID product bit 2 for USB descriptor either test pin Either ID product bit 3 for USB descriptor either test pin Either ID product bit 1 for USB descriptor either test pin Either ID product bit 0 for USB descriptor either test pin Initialisation input pin, zero active. Digital input supply, must be connected to VREGD1
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ST5481
Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Name GNDD2 CFG0_TEST0 FLTPLL XTALOUT XTALIN GPIO0 GPIO1 GPIO2 GPIO3 GNDD1 GPIO4 GPIO5 GPIO6 GPIO7
Type I I/O In analog O I I/O I/O I/O I/O I I/O I/O I/O I/O Digital ground
Function
CFG0 input for configuration when closed or open mode else test9 Used to adjust the internal PLL filter Tied to 15.36MHz external crystal Tied to 15.36MHz external crystal General purpose input-output pin 2mA General purpose input-output pin 2mA General purpose input-output pin 2mA General purpose input-output pin 2mA Digital ground General purpose input-output pin 4mA General purpose input-output pin 4mA General purpose input-output pin 4mA General purpose input-output pin 4mA
3.2 - PLL An internal oscillator provides a 15.36MHz clock for S interface from an external 15.36MHz crystal. From this clock, the analog block PLL provides a 48MHz clock for USB data rate recovering.
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ST5481
4 - SYNOPTIC Figure 2 : Global Synoptic
VREF-GEN
VREF IREF NRESET S0 4 S0 interface TXCK_O RXCK_O TXFS_O RXFS_O TXDATA RXDATA B1_W FLTPLL PLL 48MHz 15.36 15.36MHz CK48 STOP_OSC MCLK B2_W D_W NLSD DEN Descriptor ROM 256 bytes 4 USB Bus CHANNEL ACCESS and FRAMING B1, B2, D FIFOS for isochonous endpoints CONTROL_DATA_OUT(7-0) CONTROL_DATA_IN(7-0)
USB Driver
I430 MACROCELL
DREQ
USB MACROCELL
Endpoint 1 controller Microwire interface
NINT SDO SDI SCK NCS
Endpoint 0 controller
CK48 CK12
TEST
TEST interface
TEST2-0
Power management and REGULATORS
Test pins
MODE(3-0)
RPSM
8 power pins
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ST5481
5 - ISDN ACCESS The device is directly connected to the ISDN line at S0 interface point. 4 pins are dedicated to this access: LIP, LIN: receive AMI differential signals inputs connected to the appropriate transformer LOP, LON: transmit AMI differential signals outputs connected to the appropriate transformer. The S interface access sub-function is clockfeeded by a 15.36MHz clock signal from the on-chip oscillator. I431 recommendation protocols are fully implemented. The activation / deactivation command management is done by the device. 5.1 - ISDN S Interface Synoptic See Figure 3. 6 - USB ACCESS The device is directly connected to the USB bus. 4 pins are dedicated to this access: Figure 3 : S-Interface Block Diagram DP, DM for data exchange. VBUS, GNDBUS as power lines. The data transfer rate is 12 MBits. The clock is extracted from the differential lines DP, DM by a digital PLL from a 48MHz internal clock. This 48MHz clock is created from the 15.36MHz clock. The USB protocol is fully implemented following the 1.0 USB specification. 6.1 - USB Normalization This specification refers to USB normalization documents: - Universal Serial Bus Specification revision 1.0 - Universal Serial Bus Common Class Specification revision 1.0 - ST5481 belongs to the VENDOR SPECIFIC DEVICE CLASS and to a vendor specific subclass defined as ISDN MODEM DEVICE SUBCLASS. It presents ONE INTERFACE belonging to the VENDOR SPECIFIC INTERFACE CLASS and a vendor specific interface subclass defined as ISDN SOFT MODEM INTERFACE SUBCLASS. It satisfies to a vendor specific control protocol called ISDN SOFT MODEM PROTOCOL.
- Tx multiframe control - D channel monitoring - Loopbacks - Frame construction - AMI code generation Line Driver
TXNUM
Line Signal Detector
- C/I control - Activation state machine - Master clocks generation - D & E channel processing
- Auto threshold controller - Auto equalizer controller - Digital PLL, line synchronization - AMI decoder - Frame synchronization & polarity check - Signal ID - Multiframe control. RXNUM
Pre Filter & equalizer
Rx
Slicers
CONTROL
2x6 bits DACs
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ST5481
7 - POWER MANAGEMENT The device can be supplied by the USB bus power lines VBUS (5 volts) and GNDBUS (ground). This is enabled when RPSM (remote power supply mode) is at logic one. Then on-chip regulators bring 3.3 volts to internal analog and digital blocks. When RPSM is high, a supply is brought to external devices through pins GNDD1, VREGD1, GNDD2, VREGD2, GNDA, VREGA. Figure 4 : Bus-Powered Mode (RPSM=1)
4 8 5 From USB bus 3 4 GNDBUS VREGD1 RPSM 44 VBUS From 3.3V externally regulated supplies 34 GNDD1 VREGD2 VREGD1
Figure 5 : Self Powered Mode (RPSM=0)
8 5 From USB bus 3
RPSM VBUS
GNDBUS
35 6
GNDD2 VREGA
To other digital device
44 34
GNDD1 VREGD2
7
GNDA ST 5481
35 6 To other analog device
GNDD2 VREGA GNDA ST 5481
The power budgeting is done by the host when initializing the pipe: The needed information (maximum power consumption) is adjusted through pins CFG0, CFG1 and as well as RPSM for "remote wake up ability" information. The following mechanism is used to do "a get description device".
7
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ST5481
The host gets back the configuration of the device either a low power device, either a high power device (max power parameter higher than 100mA). Being a high power device allows to set on a wake up ability because looking for a line signal detection consume more than 500uA allowed for a low power device when in a suspend state. To adjust the maximum power consumption parameter into the configuration descriptor, the logical values present on pins CFG0, CFG1, RPSM are used (see Table 1). At power on, the digital regulator is immediately ON and after 100s the analog regulator is authorized to feed the internal oscillator. - Initialization and clocks management. - A HARDWARE PIN RESET is done through pin NRESET (active low). - A delay of 4.5ms is introduced before distributing the clocks to the internal functions. - A USB HARDWARE RESET is done through DP, DM pins. This reset affects the USB interface, resetting the USB core state machines. It does not affect the application (S interface, registers, fifos). A USB SOFTWARE RESET is done through USB bmRequest SET_DEFAULT. It brings the S interface, application registers, application state machines and fifos pointers to default state. When the device goes out of SUSPEND_CLOCK state, a delay of 4.5ms is introduced before distributing the clocks to the internal functions. When the device enters into a suspend mode due to inactivity on USB bus, the oscillator is stopped in order to save power except if FCONF(3) is equal to 1.
Table 1 : Maximum Power Current and Wake up Ability Coding
Max Power Current 100 mA 150 mA 150 mA 250 mA 100 mA 150 mA 150 mA 250 mA High/Low Power LO HI HI HI LO HI HI HI Wake Up Ability NO NO YES YES NO NO YES YES CFG1 0 0 1 1 0 0 1 1 CFG0 0 1 0 1 0 1 0 1 RPSM 1 1 1 1 0 0 0 0 Bm Attributes ROM add 27 80 80 A0 A0 C0 C0 E0 E0 Max Power ROM add 28 32 96 96 F9 32 96 96 F9
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ST5481
8 - DEVICE STATES The device complies with USB rev 1.1 power management requirements. It complies with requirements. I430 power management It means that S interface cannot be activated neither by the host nor by a detection of signal on line. This signal detection is disabled. The 15MHz oscillator is not addressed to MACRO-S M2: ACTIVE Mode. When the device is in S6,S7,S8,S9 states from USB point of view, the S interface may be in this state, then it can be deactivated by a PDN primitive (from host) or a hardware power down which is generated by a suspend event on USB bus M3: INACTIVE Mode (initial mode if CFG1 = 1). The line signal detection is enabled. Then it can be activated (go to state ACTIVE) by a line signal detection. When USB is suspended, The S interface will really be in the active mode once a resume signalling has been done on USB bus after the NLSD signal became active. When USB is configured, a transition from this mode to ACTIVE mode is obtained with a PUP primitive (from host).
Due to inactivity on the USB bus for more than 3 ms, the device may enter into the SUSPEND mode even if Reset signalling is not done yet. The ST5481 recovers activity within the 15ms of the resume signalling issued by the host or hub. If wake up is enabled and occurs, the ST5481 recovers activity within the 15ms when it initiates the resume (K state) and about the same time the host or hub initiates a Reset (SEO for 10 ms). Wake up ability concerns wake up of the USB bus (resume event when the bus is in a suspend state) from the S line through a line signal detection done by the S interface. Interface S states and relationship with Device versus USB States. M1: QUIET mode (initial mode if CFG1 = 0). Figure 6 : S Interface States - CFG1=0
PON RESET / USB REQUEST/ PIN RESET
M1 OFF S LINE ACTIVATION NOT POSSIBLE
STT(5)=1
STT(5)=1 STT(5)=0
PUP or NLSD=0 M2 ACTIVE M3 INACTIVE S LINE ACTIVATION POSSIBLE PDN or PDWN=1
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ST5481
If Pin CFG1 is 1, when reset (PON,USB,PIN) is active the initial state is INACTIVE. Figure 7 : S Interface States - CFG1=1
M1 OFF OFFS LINE ACTIVATION NOT POSSIBLE
PON RESET / USB REQUEST/ PIN RESET STT(5)=1
STT(5)=1
STT(5)=0
PUP or NLSD=0 M2 ACTIVE M3 INACTIVE S LINE ACTIVATION POSSIBLE PDN or PDWN=1
9 - ENDPOINTS CONFIGURATION AND DEDICATION These endpoints are organized as one interface (interface 0), one configuration (configuration 1). The interface being composed of four alternate settings. Hereafter in the document RX data direction is from S line to PC and is considered as IN by USB protocol. The endpoints are: - 4 isochronous endpoints for B1 and B2 channels (fifo 32 bytes in each direction) - 1 control endpoint means management of USB standards, Communication Device Class (CDC) standards (unused), and vendor requests (S interface application dedicated):
*
EP0 - internal configuration and control registers - D, B1, B2 channels transmit commands - CI primitives to be transmitted
* * * *
EP3 input endpoint for B1 channel IN(RX) on S line - associated to IN(RX) fifo 32 bytes EP2 output endpoint for B1 channel OUT(TX) on S line - associated to OUT(TX) fifo 32 bytes EP5 input endpoint for B2 channel IN(RX) on S line - associated to IN(RX) fifo 32 bytes
- 1 interrupt endpoint used for vendor interrupts
*
EP1 - channels reception or transmission indications - CI primitives in receive direction - D, B1, B2 channel reception indications - S line status - GPIO input changes
The alternate settings are:
EP4 output endpoint for B2 channel OUT(TX) on S line - associated to OUT(TX) fifo 32 bytes - 2 isochronous endpoints for D channels (fifo 16 bytes in each direction)
* * * *
Alternate setting 0: EP0, EP1. - initialisation configuration Alternate setting 1: EP0, EP1, EP2, EP3, P6, EP7 - connection 64Kbits through B1 channel Alternate setting 2: EP0, EP1, EP4, EP5, EP6, EP7 - connection 64Kbits through B2 channel Alternate setting 3: EP0, EP1, EP2, EP3, EP4, EP5, EP6, EP7 - connection 128Kbps (144Kbits/sec) through B1 + B2 + (data into D) channels
* *
EP7 input endpoint for D channel IN(RX) on S line - associated to IN(RX) fifo 16 bytes EP6 output endpoint for D channel OUT(TX) on S line - associated to OUT(TX) fifo 16 bytes
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ST5481
USB Descriptors During the USB request GET DESCRIPTOR, the device returns these values from an internal 256 byte ROM. Table 2 : Device Descriptor
ROM addr 08 09 0A 0C 0D 0E 0F 10 12 14 16 17 18 19 Offset 0 1 2 4 5 6 7 8 10 12 14 15 16 17 bLengh bDescriptorType bcdUSB bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 idVendor idProduct bcdDevice iManufacturer iProduct iSerialNumber bNumConfigurations Field Size 1 1 2 1 1 1 1 2 2 2 1 1 1 1 Value 12h 01h 0101h FFh 01h 01h 08h 0483h 481xh 01xxh 00h 01h 00h 01h Description Size of this descriptor in bytes Device Descriptor type USB spec release number 1.1 Vendor Specific Class code Vendor specific ISDN MODEM subclass Vendor specific ISDN SOFT MODEM control protocol Max packet size for EP0 ST id vendor Application id product 1 Device release 2 No specific manufacturer registred product id String descriptor index 1 No specific serial number registred Number of possible configurations
Notes 1. This word represents the hardware-software association. The value is programmable through 4 of the 16 bits. the lower bits values are defined by pins ID3 to ID0. 2. This word represents the silicon hardware. The lower 8-bit value is defined at metal layer. The other 8 bits are written into the ROM at diffusion layer.
Table 3 : Interface 0 as 0 Descriptor
ROM addr 20 21 22 24 25 26 27 28
Note
Offset 0 1 2 4 5 6 7 8 bLengh
Field
Size 1 1 2 1 1 1 1
Value 09h 02h
Description Size of this descriptor in bytes Configuration Descriptor type
bDescriptorType wTotalLengh bNumInterface bConfigurationValue iConfiguration bmAttributes MaxPower
00CFh Total length of data byte returned for this configuration 01h 01h 00h XXh number of interfaces supported by this configuration value used to select this conf. No specific string descriptor for this configuration Self powered and remote wake-up abilities programmable 1 max consumption programmable 1
1
XXh
1. Theses words are defined by a transcoding of the pins CFG0, CFG1, RPSM : see power management section for coding of these pins.
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ST5481
10 - ELECTRICAL SPECIFICATIONS Unless otherwise stated, electrical characteristics are specified over the operating range. Typical values are given for VBUS = +5V, VregA = 3.3V, VregD1 = VregD2 = 3.3V, Tamb = 25C 10.1 - Absolute Maximum Rating Table 4 : Absolute maximum ratings
Symbol VBUS VREGD1 VREGD2 VREGA VIA VID VID Toper Tstg Parameter 5V Power Supply Voltage 3.3V Power Supply Voltage 1 3.3V Power Supply Voltage 1 3.3V Power Supply Voltage 1 Analog Input Voltage 2 Digital Input Voltage Digital Input Voltage on RPSM Operating Temperature Storage Temperature Value 5.5V -0.3V to 3.6V -0.3V to 3.6V -0.3V to 3.6V -0.3 to VREGA + 0.3V -0.3 to VREGDX + 0.3V -0.5 to VBUS + 0.3V 0, +70 -55, +125 C Unit V V V V V V V C C
Notes GNDA = GNDD1 = GNDD2 = GNDBUS = 0V Warning : Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 1. In Remote Power Supply Mode (RPSM=0) 2. For the ISDN S side access "LOP,LON,LIP,LIN" pins the voltage level can temporary exceed the maximum rating due to the phone line conditions. To prevent any damage to the circuit, an external protection circuit must be implemented according to the application schematics.
10.2 - Nominal DC Characteristics (Ta = 0 to 70C unless otherwise specified) Table 5 : Nominal DC characteristics
Symbol VBUS Ivdd Ivdds VREGA VREGD1 VREGD2 IVregA IVregD1 IVregD2 PDLP PD
Note
Parameter Supply voltage Supply Current (RPSM=1) Supply Current in Suspended Mode (RPSM=1) Analog regulated OUTPUT power supply (RPSM=1) Analog regulated INPUT power supply (RPSM=0) Digital regulated OUTPUT power supply (RPSM=1) Digital regulated INPUT power supply (RPSM=0) Digital regulated INPUT power supply 1 Analog regulated OUTPUT current (RPSM=1) Analog regulated INPUT current (RPSM=0) Digital regulated OUTPUT current (RPSM=1) Digital regulated INPUT current (RPSM=0) Digital regulated INPUT current 1 Low Power mode (Suspended mode) Operating Power
Minimum 4
Typical 5 TBD
Maximum 5.25 TBD TBD 3.3+5% 3.3+5% 3.3+5% 40 40
Unit V mA mA V V V mA mA mA mW mW
3.3-5% 3.3-5% 3.3-5%
3.3 3.3 3.3 TBD
TBD TBD TBD TBD
1. VREGD2 is always an analog power input, to be connected to VREGD1
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ST5481
A 2.2F decoupling polarized capacitor (tantal or chemical) is necessary as between VREGA and GNDA. A 1F decoupling polarized capacitor (tantal or chemical) is necessary as between VREGD1 and GNDD1. A 1F decoupling polarized capacitor (tantal or chemical) is necessary as between VREGD2 and GNDD2. Table 6 : Digital Pins (except GPIO4 to GPIO7,XTALin, XTALout, RPSM, NRESET)
Symbol VIL VIH VOL VOH ILEAK IOL IOH VHYST CIN Low level input voltage High level input voltage Low level input voltage (ILoad = 2mA) High Level Output Voltage (Iload = -2mA) Input Leakage Current Low level input Current (0Table 7 : GPIO4, GPIO5, GPIO6, GPIO7.
Symbol VIL VIH VOL VOH ILEAK IOL IOH VHYST CIN Low level input voltage High level input voltage Low level input voltage (Iload = 2mA) High Level Output Voltage (Iload = -2mA) Input Leakage Current Low level input Current (0Table 8 : RPSM, NRESET.(5 volt inputs compatible)
Symbol VIL VIH VHYST
Note
Parameter Low level input voltage High level input voltage Schmitt Trigger Hysteresis
Minimum
Typical
Maximum 0.3VBUS
Unit V V
0.7VBUS 1 1.3
V
A 10ms time constant will be used (ex: 470 nF, 20) to generate an adequate pulse on NRESET pin.
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ST5481
Table 9 : Crystal Oscillator (XTALin, XTALout)
Symbol VIL VIH IL IH ESR CO
Note
Parameter Low level input voltage High level input voltage Low level input Current High Level Output Current Electrical Serial Resistor Shunt capacitance
Minimum
Typical
Maximum 0.2VRegD1
Unit V V uA
0.8VRegD1 -TBD TBD 25 7
uA pF
Manufacturer example: Ref MMD A20BA1- 15.36MHz
Table 10 : 48MHz Internal PLL
Symbol JiTTER Lock Time Parameter Jitter peak-peak Magnitude High level input voltage Minimum Typical 0.35 60 Maximum 5 100 Unit ns us
10.3 - Universal Serial Bus Interface See Chapter 7 of USB rev1.0 for complete Electrical Specification Table 11 : USB Nominal DC Characteristics (DP, DM)
Symbol VDI VCM VSE VOH VOL ILO Cin RD Parameter Differential Input Sensitivity [(DP)-(DM)] Differential Common Mode Range Single Ended Receiver Threshold High Level output Static voltage (RL of 15K to GND) Low level input Static voltage (RL of 1.5K to 3.6V) Hi-Z State Data Line Leakage Current (0v See Chapter 7 of USB rev1.0 for complete Electrical Specification.
Note Excludes external resistor. In order to comply with USB Specification 1.0, external series resistors of 27 1% each on DP and DM are recommended.
AC Characteristics (DP, DM) See Chapter 7.3.2 of USB rev1.0 for complete Electrical Specification.
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ST5481
10.4 - Line Side Isdn S Interface Table 12 : ISDN Interface Electrical Characteristics: RIREF = 120k
Symbol ITX ITX ITX ZOTX Parameter TX Line Driver current with 70 between LOP / LON [ 70 (total)= 50 (load) + 2 x 7 (serial) + 2 x 3 (serial) ] TX Line Driver current with 420 between LOP / LON [ 420 (total)= 400 (load) + 2 x 7 (serial) + 2 x 3 (serial) ] TX Line Driver current with 25.6 between LOP / LON [ 25.6(total)= 5.6 (load) + 2 x 7 (serial) + 2 x 3 (serial) ] Transmit Output impedance during pulse. ( 20 is obtained as total min value with serial resistors: [ 20(total)= ZOTX+ 7(serial) + 7(serial) ]) Impedance when inactive, between LOP / LON Receive Input impedance between LIP / LIN 6 Minimum 14.25 Typical 15 Maximum 15.75 3 26 Unit mA mA mA k
ZTX ZINRX
Note
2.5 2.5
k k
UIT-TI430, ETSI 300012, ANSI T1.605 standards compliance.
11 - APPLICATION SYNOPTIC 11.1 - Global Environment Figure 8 : Synoptic
USB Plug B Usb cable
ISDN USB dongle RJ45 ST5481 S interface NT1
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gpio7
gpio6
gpio5
gpio4
gpio3
gpio2
gpio1
gpio0
xtalin
11.2 - Application Schematic
1 1 VCC 2 3 VCC R18 6 VregA GndA rpsm mode0 mode1 mode2 mode3 U1 ST5481 4.7M 7 8 + C7 10F + 10 11 12 GNDA R17 120K GND.D1/D2 2.2F C8 100nF C10 9 5 Vbus id0/test15 32 id1/test14 31 id3/test1 30 id2/test2 29 clk/test3 28 fs/test4 27 dr/test5 26 dx/test6 25 4 Vregd1 nreset 33 Gndbus Vregd2 34 DP Gndd2 35 DM Cfg0/test0 36
2
3
Gndd1
xtalout
D+in
GND
D-in
fltpll
lip
lin
iref
lon
lop
test12
test13
ncs/test11
sdi/test10
cfg1/test9
sd0/test8
13
14
15
16
17
18
19
20
21
22
23
24
sck/test7
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L1 4.7H D1 LED R1 510 Y1 R7 1K C1 47pF 48 47 46 45 44 43 42 41 40 39 38 37 C2 33pF C3 33pF 15.36MHz VCC R21 510 D2 LED 4 D-out 6 D+out U2 USBUF01W6 VCC 5 R2 220K + C9 4.7F C4 100nF R15 1M T1 R19 4 I/03 U3 ref1 DALC208SC6 ref2 I/04 1 2 I/01 I/02 5 6 3 4.7 2 1 R20 4.7 T60407 L526X010 D3 SMLTV3/3 R23 12 10K 1% 6 C11 100nF R22 10K 1% 7 9 8 11 2fold-Choke 2x5mH 10 2:1 5 4 5 6 7 8 RJ45 15 14 13 2fold-Choke 2x5mH 16 2:1 2 3 4 1 2 3 J2 1
J1
1
D-
ST5481
2
USB-B
D+
3
4
6
5
R16
Figure 9 : Schematic
0
ST5481
TQFP48 PACKAGE MECHANICAL DATA Figure 10 : 48 Pins - Full Plastic
A A2 48 1 e A1 37 36 0,10 mm .004 inch SEATING PLANE B 12 13 24 25
c
D3 D1 D
L1
L
E3 E1 E
K
0,25 mm .010 inch GAGE PLANE
Millimeter Dimension Minimum A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.17 0.09 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 0 (minimum), 7 (maximum) 0.75 0.018 1.40 0.22 Typical Maximum 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 Minimum
Inch Typical Maximum 0.063 0.006 0.055 0.009 0.057 0.011 0.008 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039 0.030
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ST5481.REF
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